The invention relates to a circuit arrangement for pulse generation.
Circuit arrangements having a pulse duration dependent on the charging current of a capacitor have, inter alia, the advantage that the pulse duration may be set within wide limits. To achieve stability of the pulse duration set in each case, it is important, in addition to the stability of the voltage rise at the capacitor, also to keep constant the offset or the voltage at the capacitor between the pulses. This lower threshold is especially necessary if a semiconductor layer serves as capacitor plate in integrated circuits and the capacitor exhibits constant capacitance only from a minimum voltage.
It is an object of the invention to provide a circuit arrangement in which this offset is kept constant.
This object is achieved according to the invention in that
a charging current and a discharging current may be supplied in succession to a capacitor, with a threshold value switch connected to the capacitor and a bistable circuit connected to the threshold value switch, the output of which bistable circuit outputs a switching signal during supply of the charging current,
a current source, a first current mirror circuit and a second current mirror circuit complementary to the first current mirror circuit are provided to generate the charging current and the discharging current,
the first current mirror circuit comprises an input transistor and three output transistors connected with the gate electrodes thereof, wherein the first of the output transistors comprises a larger area than the second and third output transistors,
the drain electrodes of the first output transistor and an input transistor of the second current mirror circuit are connected together,
the drain electrodes of the second output transistor of the first current mirror circuit and an output transistor of the second current mirror circuit are connected together, to the capacitor and to an input of a regulator in the form of a differential amplifier,
the third output transistor of the first current mirror circuit and a further output transistor of the second current mirror circuit are connected together to form an output stage and are connected to a circuit for controlling the tail current of the differential amplifier and
a current output of the differential amplifier is connected to the drain electrode of the output transistor of the second current mirror circuit.
With the circuit arrangement according to the invention, pulses of adjustable width may be generated, wherein the width is adjustable via corresponding control of the current source. The circuit arrangement according to the invention further exhibits the advantage that it may be easily integrated with conventional technologies. Accordingly, the circuit is preferably produced with MOS field effect transistors. However, implementation with bipolar transistors is not ruled out in principle.
In order also to keep an offset of the differential amplifier small, provision is made according to a further development for the circuit for generating the tail current of the differential amplifier to consist of a third and a fourth current mirror circuit, wherein the current supplied to the circuit is doubled.
In still a further development, particularly advantageous introduction of the control signal into the output stage and advantageous switching of the charging current are achieved in that the differential amplifier takes the form of two source-coupled transistors, wherein the switching signal may be supplied by the bistable circuit to the drain electrode of a transistor of the differential amplifier and wherein a fifth current mirror circuit is provided in the output circuit of this transistor, the output of which fifth current mirror circuit is connected with the drain electrode of the output transistor of the second current mirror circuit.
In the case of the circuit arrangement according to the invention, the current mirror circuits are assisted in functioning more accurately by an advantageous development which consists in the fact that the output transistors of the first and second current mirror circuits are each supplemented by a further transistor in cascode connection.